1. Field of the Invention
The present invention relates to an electrically writable and erasable thin film memory.
2. Description of the Related Art
The EEP ROM (Electrically Erasable and Programmable Read Only Memory) is generally known as an electrically writable and erasable memory transistor. Further, the EEP ROM is likewise known to come in an MNOS structure and a floating gate structure, both of which uses a tunnel effect. Structurally precise with the EEP ROM, over the surface of a silicon substrate, there are provided a tunnel oxide film, a charge trapping insulating film, and a gate electrode in respective layers. Functionally concrete with the EEP ROM, it is found that applying a high voltage between the gate electrode and the substrate brings forth the tunnel effect, whereby the electrons or the positive holes, collectively referred to as the charges, pass through the tunnel oxide film, and subsequently get trapped in a boundary between the tunnel oxide film and the charge trapping insulating film or another boundary between the silicon substrate and the tunnel oxide film. Trapping the charges in one of these boundaries makes the threshold voltage shift in a direction opposite to the direction in a case with the trapping the same type of the charges in another boundary. Shifting a polarity of the threshold voltage to negativity concurs with the emergence of an erased (post-erasure) state wherein a drain current occurs constantly. Meanwhile, shifting to the positive polarity of the threshold voltage signifies the presence of a written (post-write) state where no drain current obtains even an ON-voltage applied. Of particular note is a fact that the charges trapped in one of these boundaries are kept unchanged after removal of the ON-voltage. This demonstrates the physical characteristic of a non-volatile memory. However, as the conventional EEP ROM is manufactured from a silicon water, it is required to provide source regions and drain regions within a P-well, field insulating films to isolate memory transistors to each other, and so on. This causes the production process to become complex, to fail higher efficiency, and further renders an EEP ROM structure to be unfit for circuit integration.
To make up for these disadvantages, some attempts are currently under way with a view to realizing such a non-volatile memory, following the TFT technology. Though difference from the above-remarked EEP ROM over the drive procedure, a memory cell structure is disclosed in U.S. Pat. No. 4,667,217 which is considered serviceable for reference to achieve a TFT (Thin Film Transistor) memory cell. In the prior art disclosed in said U.S. Patent, the non-volatile memory device is of a TFT structure. However, with this memory device, it is of such a configuration devised for electrons only avalanche, namely of a single charge channel (N-channel) run arrangement. Therefore, there exists no feasibility to expand the width of hysteresis. In other words, no practicality is available to increase the difference between the respective threshold voltages in the post-write and post-erasure states. This coincides with not only unpracticality to grow the ratio between the respective drain currents in the written state and erased state but also low accuracy in charge potential level discrimination.